1 commercial and industrial temperature ranges idt5v9910a 3.3v low skew pll clock driver turboclock jr. september 2001 2001 integrated device technology, inc. dsc 5847/2 c commercial and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. features: ? eight zero delay outputs ? <250ps of output to output skew ? selectable positive or negative edge synchronization ? synchronous output enable ? output frequency: 15mhz to 85mhz ? 3 skew grades: idt5v9910a-2: t skew0 <250ps idt5v9910a-5: t skew0 <500ps idt5v9910a-7: t skew0 <750ps ? 3-level inputs for pll range control ? pll bypass for dc testing ? external feedback, internal loop filter ? 12ma balanced drive outputs ? low jitter: <200ps peak-to-peak ? available in soic package functional block diagram gnd/soe q 0 q 1 ref fs pll fb v ccq /pe q 2 q 3 q 4 q 5 q 6 q 7 idt5v9910a 3.3v low skew pll clock driver turboclock? jr. description: the idt5v9910a is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications appli- cations. it has eight zero delay lvttl outputs. when the gnd/ soe pin is held low, all the outputs are synchronously enabled. however, if gnd/ soe is held high, all the outputs except q 2 and q 3 are synchronously disabled. furthermore, when the v ccq /pe is held high, all the outputs are synchronized with the positive edge of the ref clock input. when v ccq / pe is held low, all the outputs are synchronized with the negative edge of ref. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
2 commercial and industrial temperature ranges idt5v9910a 3.3v low skew pll clock driver turboclock jr. pin configuration note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit supply voltage to ground ?0.5 to +7 v v i dc input voltage ?0.5 to v cc +0.5 v ref input voltage ?0.5 to +5.5 v maximum power dissipation (t a = 85c) 530 mw t stg storage temperature ?65 to +150 c note: 1. capacitance applies to all inputs except test and fs. it is characterized but not production tested. capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance 5 7 pf pin description pin name type description ref i n reference clock input fb i n feedback input test (1) i n when mid or high, disables pll (except for conditions of note 1). ref goes to all outputs. set low for normal operation. gnd/ soe (1) i n synchronous output enable. when high, it stops clock outputs (except q 2 and q 3 ) in a low state - q 2 and q 3 may be used as the feedback signal to maintain phase lock. set gnd/ soe low for normal operation. v ccq /pe i n selectable positive or negative edge control. when low/high the outputs are synchronized with the negative/positive edge of the reference clock. fs (2) i n frequency range select: fs = gnd: 15 to 35mhz fs = mid (or open): 25 to 60mhz fs = v cc : 40 to 85mhz q 0 - q 7 out eight clock output v ccn pwr power supply for output buffers v ccq pwr power supply for phase locked loop and other internal circuitry gnd pwr ground soic top view notes: 1. when test = mid and gnd/ soe = high, pll remains active. 2. this input is wired to vcc, gnd, or unconnected. default is mid level. if it is switched in the real time mode, the outputs may glitch, and the pll may require an additional lock time before all data sheet limits are achieved. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ref fs nc v ccq /pe q 0 q 1 gnd q 2 q 3 gnd test nc gnd/soe q 7 q 6 gnd q 5 q 4 fb v ccn v ccn v ccq v ccn v ccn
3 commercial and industrial temperature ranges idt5v9910a 3.3v low skew pll clock driver turboclock jr. recommended operating range idt5v9910a-5, -7 idt5v9910a-2 (industrial) (commercial) symbol description min. max. min. max. unit v cc power supply voltage 3 3.6 3 3.6 v t a ambient operating temperature -40 +85 0 +70 c power supply characteristics symbol parameter test conditions (1) typ. (2) max. unit i ccq quiescent power supply current v cc = max., test = mid, ref = low, 8 25 ma gnd/ soe = low, all outputs unloaded ? i cc power supply current per input high v cc = max., v in = 3v 1 30 a i ccd dynamic power supply current per output v cc = max., c l = 0pf 55 90 a/mhz i tot total power supply current v cc = 3.3v, f ref = 25mhz, c l = 160pf (1) 34 ? v cc = 3.3v, f ref = 33mhz, c l = 160pf (1) 42 ? m a v cc = 3.3v, f ref = 66mhz, c l = 160pf (1) 76 ? note: 1. for eight outputs, each loaded with 20pf. dc electrical characteristics over operating range symbol parameter conditions min. max. unit v ih input high voltage guaranteed logic high (ref, fb inputs only) 2 ? v v il input low voltage guaranteed logic low (ref, fb inputs only) ? 0.8 v v ihh input high voltage (1) 3-level inputs only v cc ? 0.6 ? v v imm input mid voltage (1) 3-level inputs only v cc /2 ? 0.3 v cc /2+0.3 v v ill input low voltage (1) 3-level inputs only ? 0.6 v i in input leakage current v in = v cc or gnd ? 5 a (ref, fb inputs only) v cc = max. v in = v cc high level ? 200 i 3 3-level input dc current (test, fs) v in = v cc /2 mid level ? 50 a v in = gnd low level ? 200 i pu input pull-up current (v ccq /pe) v cc = max., v in = gnd ? 100 a i pd input pull-down current (gnd/ soe )v cc = max., v in = v cc ? 100 a v oh output high voltage v cc = min., i oh = ? 12ma 2.4 ? v v ol output low voltage v cc = min., i ol = 12ma ? 0.55 v note: 1. these inputs are normally wired to v cc , gnd, or unconnected. internal termination resistors bias unconnected inputs to v cc /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved.
4 commercial and industrial temperature ranges idt5v9910a 3.3v low skew pll clock driver turboclock jr. input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall times, 0.8v to 2v ? 10 ns/v t pwc input clock pulse, high or low 3 ? ns d h input duty cycle 10 90 % r ef reference clock input 15 85 mhz note: 1. where pulse width implied by d h is less than t pwc limit, t pwc limit applies. switching characteristics over operating range idt5v9910a-2 idt5v9910a-5 idt5v9910a-7 symbol parameter min. typ. max. min. typ. max. min. typ. max. unit fs = low 15 ? 35 15 ? 35 15 ? 35 f ref ref frequency range fs = med 25 ? 60 25 ? 60 25 ? 60 mhz fs = high 40 ? 85 40 ? 85 40 ? 85 t rpwh ref pulse width high (8) 3? ? 3??3??ns t rpwl ref pulse width low (8) 3? ? 3??3??ns t skew0 zero output skew (all outputs) (1,3,4) ? 0.1 0.25 ? 0.25 0.5 ? 0.3 0.75 ns t dev device-to-device skew (1,2,5) ? ? 0.75 ? ? 1.25 ? ? 1.65 ns t pd ref input to fb propagation delay (1,7) ? 0.25 0 0.25 ? 0.5 0 0.5 ? 0.7 0 0.7 ns t odcv output duty cycle variation from 50% (1) ? 1.2 0 1.2 ? 1.2 0 1.2 ? 1.2 0 1.2 ns t orise output rise time (1) 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns t ofall output fall time (1) 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns t lock pll lock time (1,6) ? ? 0.5 ? ? 0.5 ? ? 0.5 ms t jr cycle-to-cycle output jitter (1) r m s ? ? 25 ? ? 25 ? ? 25 ps peak-to-peak ? ? 200 ? ? 200 ? ? 200 notes: 1. all timing and jitter tolerances apply for f nom > 25mhz. 2. skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. t skew is the skew between all outlets. see ac test loads. 4. for idt5v9910a-2 t skew0 is measured with c l = 0pf; for c l = 20pf, t skew0 = 0.35ns max. 5. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) 6. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. 7. t pd is measured with ref input rise and fall times (from 0.8v to 2v ) of 1ns. 8. refer to input timing requirements for more detail.
5 commercial and industrial temperature ranges idt5v9910a 3.3v low skew pll clock driver turboclock jr. 150 ? 150 ? v cc output 2.0v t orise t ofall 0.8v 1ns 1ns 2.0v 0.8v 3.0v 0v vth =1.5v 20pf ref fb q other q t ref t pd t skew t jr t odcv t rpwh t rpwl t skew t odcv ac test loads and waveforms test load lvttl input test waveform lvttl output waveform ac timing diagram notes: skew: the time between the earliest and the latest output transition among all outputs when all are loaded with 20pf and terminated w ith 75 ? to v cc /2. t skew : the skew between all outputs. t dev : the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. t orise and t ofall are measured between 0.8v and 2v. t lock : the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
6 commercial and industrial temperature ranges idt5v9910a 3.3v low skew pll clock driver turboclock jr. ordering information idt xxxxx x package process device type blank i 5v9910a-2 5v9910a-5 5v9910a-7 3.3v low skew pll clock driver turboclock jr. small outline ic (300-mil) soic - green so sog commercial (0c to +70c) industrial (-40c to +85c) xx corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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